Elevating Visions,
Engineering Excellence.

At Noksha Semi, we specialize in creating tailored semiconductor solutions that redefine possibilities, driving industries forward with precision and innovation.


Our Services

Analog Design Services

In Noksha Semi, we have a team of highly experienced engineers having a deep understanding and work experience in commercial analog IC design. Using state-of-the-art technology and industry-leading CAD tools, we are confident to deliver all your analog design needs, from Schematic creation to Layout design and validation.  Aside from our design team, we also have a dedicated team of R&D engineers who are constantly developing better architecture and design methods for high speed, power efficient analog ICs to keep up with the fast pacing IC world.

Analog Circuit Design and Simulation

Analog Layout Design and Simulation

Physical Verification of Designs

EDA Process & Workflow Automation

Post-Silicon Validation

IC Design Services

Semiconductor design is a highly competitive and dynamic sector, pitting large established companies against new emerging ones, all seeking market-leading performance for successful designs. Design costs are rising to accommodate increased design and verification expenses, along with the utilization of the latest technology nodes. Examples of our expertise include:

Circuit Design And Simulation

Block And Full Chip Layout

Physical Verification

Post Layout Simulation

GDSII Release

Foundry Interface

Custom IC Layout Design

The IC layout design team at Noksha Semi boasts a diverse range of technology and EDA expertise. The team has been actively involved in physical layout design across various technology nodes, including 180 nm to 16nm, and the most cutting-edge technologies. We Have Expertise In:

Standard Library Cells

Memory Cells

I/O Circuits


Band Gap Reference

Analog And Digital Layout Design

Power Management Units

Low Power Custom Circuit Design

Custom SRAM/DRAM/TCAM Design

PLLs, DLLs & Oscillators

Circuit Design

The semiconductor design industry is characterized by intense competition and constant changes, with established giants facing off against emerging players, all striving for market-leading performance in their designs. Examples Of Our Expertise Include:

High-Speed IO Design

Power Management Units

Low Power Custom Circuit Design

Custom SRAM/DRAM/TCAM Design

PLLs, DLLs & Oscillators


IP Conversion: Process, Nodes & Tech.

Switching And Linear Regulators

Charge Pump Regulators

Digital Verification

Specialized in digital verification for semiconductor design, utilizing SystemVerilog and UVM methodologies. Expertise in testbench development, coverage-driven verification, and low-power verification using CPF & UPF flow.:

Digital Verification: SystemVerilog, UVM

Testbench, Testcases with self-checking

Agent, monitor, driver in UVM

Coverage-driven SoC verification

Constraint randomization SoC verification

Gate Level Simulation (GLS)

Low Power Verification: CPF & UPF

Architecture: RISCV, GIC, DM, DMA

Bus verification: AXI, APB, AHB, Wishbone

Peripheral verification: UART, SPI, I2C, GPIO

C/C++ SoC Simulator Development

Verilog, SystemVerilog, Assembly

C, C++, Python, Tcl

Physical Design

We bridge the gap between design ideas and real-world chips, ensuring efficient and reliable functionality.

RTL Synthesis: 180nm to Submicron

RTL to GDSII Physical Implementation

Physical Design Flow Development

SDC Analysis for Synthesis and PD

Low Power, Low Latency, High-Speed Designs

UPF/CPF Files for Power Intent

Low Power Techniques Implementation

Accelerating Tape-Out Timings Strategies

Timing Closure and ECO: Block/Full Chip

Crosstalk, Noise, Signal Integrity Analysis

Physical Verification: DRC, LVS, Antenna Checks

Logic Equivalency Check (LEC)

Design for Testability

Leading semiconductor design firm specializing in comprehensive Design for Testability (DFT) solutions, covering JTAG integration, scan insertion, and advanced test optimization techniques. Our expertise extends to industry-standard EDA tools, mixed-signal DFT strategies, and post-silicon diagnosis for enhanced yield and reliability.

JTAG Integration: IEEE 1149.1, 1149.6, 1687 Standards

Scan Insertion for Test Coverage

DFT Flow at Core, Block Levels

Test Point Insertion, X Bounding for Fault Detection

Boundary Scan, MBIST, LBIST Implementation

Compression Logic IPs Creation, Synthesis

ATPG, Coverage Analysis for Test Optimization

Gate Level Simulation (GLS) Post-Synthesis

Pattern Simulation, Debugging for Test Accuracy

Low Power ATPG, At-Speed Testing Strategies

Test Data Compression for Time, Data Reduction

Post-Silicon Diagnosis: Scan, Layout Aware Diagnosis

Yield Analysis, Test Program Development

Industry-Standard EDA Tools Experience

Mixed-Signal DFT Strategies: Clock, Voltage Domains

Execution Process

Collaboration with clients

We work closely with customers to deeply understand their target market, technical requirements, and technology landscape, conducting thorough research to determine the best architecture for optimal Power, Performance, and Area (PPA) outcomes in the project.

Planning and resource allocation

Noksha Semi addresses resource allocation, tape-out deadlines, project complexity, and risk mitigation to ensure high-quality, timely delivery, while emphasizing transparent communication to navigate unexpected obstacles successfully.


At Noksha Semi, execution commences post planning, involving circuit designers meeting requirements and layout designers optimizing performance via physical implementation, all while integrating feedback for a comprehensive, well-optimized design process.

Verification & Review

Noksha Semi conducts regular reviews, engaging both internal teams and customers for feedback, facilitating a thorough and informed design evolution that upholds superior quality and customer contentment.